Coding Illness

Personal blog on computer architecture, RISC-V, technical coding challenges, problems and sometime solutions. Mathematics, Arithmetic, Cryptography, Compilers, Floating-point, Compression or whatever interests me.

Moving to substack

Dear reader, This blog is moving to substack: https://fprox.substack.com/ You will find past articles (with corrections and extension...

RISC-V Vector Element Groups

RISC-V Vector extension has defined multiple ways to organize vector data over one or multiple vector registers. In this previous blog post ...

RISC-V Compressed Instructions (part 2): Zc extensions

In this second blog post on RISC-V compressed extension we will review the Zc* family of extension designed to improve code size for embedde...

RISC-V Compressed Instructions (part 1): C extension

RISC-V base ISAs (RV32I and RV64I) define 32-bit wide instructions. Those instructions follow the standard RISC instruction set architectur...

RISC-V Vector Register Groups

The RISC-V Vector Extension (RVV) defines and exploits the concept of vector register groups . This post clarifies what a register group is...

How to read a RISC-V Vector assembly instruction

In our 5 and a half blog series, RVV in a Nutshell , we presented the basics of RISC-V Vector extension (RVV 1.0), but even after this ove...

Support of half precision floating-point numbers in RISC-V ISA: Zfh and Zfhmin

Floating-point support in RISC-V ISA RISC-V does not mandate the support of any floating-point operations as part of the base ISA (RV32I and...

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